1. Field of the Invention
The invention relates to a method of fabricating a gate of a semiconductor device, and more particularly, to a method of forming a dual gate.
2. Description of the Related Art
As the semiconductor fabrication has reached to the deep sub-micron stage, a gate has to be formed with a smaller and smaller dimension, and with a faster and faster operation speed. The operation voltage is thus lowered, and consequently, to demand a change in material and fabrication to avoid any device instability.
Conventionally, in either an N-channel metal-oxide semiconductor (NMOS) or a P-channel metal-oxide semiconductor (PMOS), a gate is formed of a polysilicon layer doped with N-type ions. A tungsten silicide layer and a silicon nitride layer are then formed on the gate. While forming a PMOS, an ion implantation is performed to an N-well or an N-type substrate for adjusting the threshold voltage of the PMOS. As a consequence, a PN junction is formed to induce a depletion region. The induced depletion region induces an equivalent buried channel device to cause a short channel effect, so that problems Such as sub-threshold voltage and out-of-control of the device by its gate.
Due to the above problems, a method of doping P-type ions into a polysilicon gate of a PMOS has been developed. Thus, a complementary MOS (CMOS) comprising two gates doped in different conductive types is formed and becomes a leading trending for further development of gate fabrication. For example, the embedded dynamic random access memory (Embedded DRAM) has employs this type of gate.
FIG. 1A to FIG. 1D show a conventional method of fabricating a dual gate. In FIG. 1A, a substrate 100 is provided. Using ion implantation, an N-well 101 and a P-well 102 are formed in the substrate 100. A shallow trench isolation 103 is formed between the N-well 101 and P-well 102 for isolation. A gate oxide layer 104 is formed on the substrate 100. A polysilicon layer 105 is formed on the gate oxide layer 104. The part of the polysilicon layer 105 over the P-well 102 is covered by a photo-resist layer 106, while the other part polysilicon layer 105 over the N-well 101 is exposed. N-type ions are implanted to the exposed part of the polysilicon layer 105.
In FIG. 1B, the photo-resist layer 106 is removed. Another photo-resist layer 107 is formed to cover the part of the polysilicon layer 105 over the N-well 101, and the polysilicon layer 105 over the P-well 102 is exposed. P-type ions are implanted into the P-well 102.
In FIG. 1C, the photo-resist layer 107 is removed. A high temperature diffusion is performed to define the N-type polysilicon layer 105a on the N-well and the P-type polysilicon layer 105b on the P-well 105b. A titanium silicide layer 108 is formed on the N-type polysilicon layer 105a and the P-type polysilicon layer 105b. A silicon nitride layer 109 is formed on the titanium silicide layer 108.
In FIG. 1D, the silicon nitride layer 109, the titanium silicide layer 108, the polysilicon layers 105a and 105b are patterned to form a gate on the N-well 101 and a gate on the P-well 102.
In the above method for forming a dual gate structure, the polysilicon layer has to be doped by two ion implantation steps with the aid of forming two photo-resist layers by two photolithography processes. The fabrication process is complex, so that a long process time is consumed. In addition, two photo-resist layers are formed, so that the fabrication cost is high.